This work presents the packet synchronization in the baseband implementation of an OFDM system on a DSP board. The basic system blocks, following the design parameters of the HIPERLAN/2 standard, have been implemented. This work focuses on the packet synchronization aspects, presenting some results in terms of the packet loss probability determined by a wrong synchronization. The implementation has been tested on a Texas Instruments C64 fixed-point DSP and is part of a more general project to achieve the implementation of a OFDM transmission system, up to an IF analog output, using high speed ADCs and DACs.
DSP Implementation of Packet Synchronization for OFDM
CORVAJA, ROBERTO;
2006
Abstract
This work presents the packet synchronization in the baseband implementation of an OFDM system on a DSP board. The basic system blocks, following the design parameters of the HIPERLAN/2 standard, have been implemented. This work focuses on the packet synchronization aspects, presenting some results in terms of the packet loss probability determined by a wrong synchronization. The implementation has been tested on a Texas Instruments C64 fixed-point DSP and is part of a more general project to achieve the implementation of a OFDM transmission system, up to an IF analog output, using high speed ADCs and DACs.File in questo prodotto:
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