Most Software Defined Radio platforms use, for baseband processing, an architecture made of heterogeneous cores: a DSP, a microprocessor and an FPGA. In this paper we take as reference the DaVinci DM6446 System On Chip (SoC) from Texas Instruments, focusing on the communication between the DaVinci SoC and a Xilinx Virtex-4 SX35 FPGA. A specific platform, integrating both these chips with an RF front-end and specifically aimed at the Software defined Radio, is selected: the Lyrtech SFF SDR board. In the selected framework we compare four options for the connection of the FPGA and the DaVinci chips, namely the VLYNQ™ and EMIF interfaces, the SPI bus and the Video Processing Subsystem (VPSS). Our aim is to assess the capability of the different interfaces to sustain a high throughput without compromising the computational power of the DSP and the microprocessor. Our analysis and our experiments show that the SPI interface is the easiest way to connect the DaVinci DM6446 with the Virtex-4 FPGA, but is limited to a throughput of 8.3 Mbit/s while an innovative solution, proposed here for the first time and based on the VPSS, originally conceived to transfer video streams, is more complex to implement but can reach a throughput of 1.2Gbit/s.

Heterogeneous Cores Interconnection Techniques: the Lyrtech SFF SDR Board Example

CAMPANA, OTTAVIO;VANGELISTA, LORENZO;FANTOZZI, CARLO;VOGRIG, DANIELE
2009

Abstract

Most Software Defined Radio platforms use, for baseband processing, an architecture made of heterogeneous cores: a DSP, a microprocessor and an FPGA. In this paper we take as reference the DaVinci DM6446 System On Chip (SoC) from Texas Instruments, focusing on the communication between the DaVinci SoC and a Xilinx Virtex-4 SX35 FPGA. A specific platform, integrating both these chips with an RF front-end and specifically aimed at the Software defined Radio, is selected: the Lyrtech SFF SDR board. In the selected framework we compare four options for the connection of the FPGA and the DaVinci chips, namely the VLYNQ™ and EMIF interfaces, the SPI bus and the Video Processing Subsystem (VPSS). Our aim is to assess the capability of the different interfaces to sustain a high throughput without compromising the computational power of the DSP and the microprocessor. Our analysis and our experiments show that the SPI interface is the easiest way to connect the DaVinci DM6446 with the Virtex-4 FPGA, but is limited to a throughput of 8.3 Mbit/s while an innovative solution, proposed here for the first time and based on the VPSS, originally conceived to transfer video streams, is more complex to implement but can reach a throughput of 1.2Gbit/s.
From SDR to Cognitive Networks
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11577/188559
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