Lifetime estimation of analog circuits from the electrical characteristics of stressed MOSFETs

With the continuous scaling of MOSFET devices the gate oxide thickness has decreased drastically in the last years [1]. Unfortunately some reliability problems appear due to this scaling, such as the degradation and breakdown (BD) of the gate oxide as a consequence of the higher electrical fields in the device [2,3]. How this degradation and BD affect the performance of devices and CIs is still an open question. Although several studies have been already presented mostly on the impact of BD on digital circuits, concerning analog circuits, the degradation effects could be specially harmful [4,5]. In this work the impact of electrical stress on NMOS transistors characteristics has been analyzed. From the experimental data, an estimation of their lifetime, when working on analog circuits, at operation voltages has been done.