The paper demonstrates some techniques for the localization of parasitic paths responsible for the latch-up phenomenon in CMOS integrated circuits, based on voltage contrast or electron beam current induced current (EBIC) in a scanning electron microscope (SEM).
SEM study of latch-up in steady-state and transient conditions
ZANONI, ENRICO
1985
Abstract
The paper demonstrates some techniques for the localization of parasitic paths responsible for the latch-up phenomenon in CMOS integrated circuits, based on voltage contrast or electron beam current induced current (EBIC) in a scanning electron microscope (SEM).File in questo prodotto:
Non ci sono file associati a questo prodotto.
Pubblicazioni consigliate
I documenti in IRIS sono protetti da copyright e tutti i diritti sono riservati, salvo diversa indicazione.
