Evidence for temperature-dependent buffer-induced trapping in GaN-on-silicon power transistors

The aim of this work is to quantitatively investigate the physical origin of the temperature-dependent dynamic R<inf>on</inf> in GaN based power transistors grown on silicon substrate. The analysis is based on combined trapping/detrapping measurements. Trapping was induced by exposing the devices to two different bias points: off-state bias (V<inf>GS</inf>=-10 V, V<inf>DS</inf>=100 V, and V<inf>B</inf>=0 V), and backgating bias (V<inf>GS</inf>=0 V, V<inf>DS</inf>=0 V, and V<inf>B</inf>=-100 V). The experimental data collected within this paper demonstrate the following relevant results: (i) when submitted to high temperature levels, dynamic R<inf>on</inf> shows a significant increase; (ii) combined off-state stress and backgating tests suggest that trapping proceeds through the injection of electrons from the buffer towards traps located in the GaN, next to the channel region; (iii) the temperature-dependent dynamic R<inf>on</inf> can be significantly reduced through the optimization of the growth and fabrication process. © 2015 IEEE.