In this paper we describe a parallel architecture for motion estimation based on the Full Search Block Matching Algorithm. The distinctive characteristic of the proposed architecture is its suitability to be implemented both in a high performance dedicated device for embedded systems (e.g. an ASIC) and on mesh connected SIMD massively parallel computers. The paper describes the first of these options in detail. © Springer-Verlag Berlin Heidelberg 1995.
A VLSI scalable processor array for motion estimation
MARESCA, MASSIMO;MIGLIARDI, MAURO
1995
Abstract
In this paper we describe a parallel architecture for motion estimation based on the Full Search Block Matching Algorithm. The distinctive characteristic of the proposed architecture is its suitability to be implemented both in a high performance dedicated device for embedded systems (e.g. an ASIC) and on mesh connected SIMD massively parallel computers. The paper describes the first of these options in detail. © Springer-Verlag Berlin Heidelberg 1995.File in questo prodotto:
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