A 39-GHz Frequency Tripler with >40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS

The generation of the carrier signal with a very low spur level is a key challenge in all the communication systems,especially those operating at mm-waves,where a frequency multiplier is typically used to break the tradeoff between high frequency of operation and low phase noise. This letter describes a frequency tripler tailored to cover the fifth generation new radio 39-GHz frequency range. By embracing the edge-combining concept,together with the combination of a single-stage polyphase filter and a multipoint injection-locked ring oscillator,the proposed frequency multiplier is able to offer robust and consistent high harmonic rejection ratio over a large fractional bandwidth. Fabricated in 28-nm bulk CMOS technology,the measured frequency multiplier features >40-dBc harmonic rejection over an outstanding 35% fractional bandwidth,while consuming 25 mW only from 0.9-V supply. To the best of our knowledge,the proposed multiplier achieves the highest harmonic rejection among the state-of-the-art multipliers in CMOS and BiCMOS technologies,while having 60% smaller area.