This paper presents an octacore DCO, implemented in a 28 nm CMOS technology, able to achieve an outstanding phase noise performance: -126 dBc/Hz at 1 MHz offset from the 10.7 GHz carrier with 173 mW power consumption. The design is scalable, as the network coupling the oscillator cores can be reconfigured allowing to switch off some cores to save power without incurring in any additional phase noise penalty other than the one expected from the reduction of the number of the active cores. The DCO achieves a 27% tuning range with 6 MHz frequency resolution.

A 10.7-14.1 GHz Reconfigurable Octacore DCO with -126 dBc/Hz Phase Noise at 1 MHz offset in 28 nm CMOS

Tomasin L.
;
Bevilacqua A.
2021

Abstract

This paper presents an octacore DCO, implemented in a 28 nm CMOS technology, able to achieve an outstanding phase noise performance: -126 dBc/Hz at 1 MHz offset from the 10.7 GHz carrier with 173 mW power consumption. The design is scalable, as the network coupling the oscillator cores can be reconfigured allowing to switch off some cores to save power without incurring in any additional phase noise penalty other than the one expected from the reduction of the number of the active cores. The DCO achieves a 27% tuning range with 6 MHz frequency resolution.
2021
Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium
978-1-6654-2549-0
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11577/3397673
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