Analysis and Design of Ultra-Low Phase Noise Building Blocks in CMOS Technology for Wi-Fi 7 Digital PLLs

An investigation on how to realized ultra-low phase noise building blocks for the next generation Wi-Fi 7 Digital PLLs is carried out. Class-B and class-C digitally-controlled oscillators are analyzed and design procedures to reduce the flicker noise upconversion are presented. The investigation of a DTC-based fractional frequency divider follows. The phase noise limitations due to the nonidealities of the DTC are pointed out and a designed strategy to achieve an ultra-low phase noise performance is proposed. Finally, a new DTC topology is presented. Thanks to the intrinsic robustness with respect to the nonlinearities arising from the voltage dependence of the charging capacitor and the current sources, this topology is capable to achieve state-of-the-art DNL-INL performance.