Analysis of the impact of intra-die variance on clock-skew

In this work, we analyze the impact of local process variations on the clock skew of VLSI circuits designed in deep sub-micron technologies. As the size of active repeaters decreases, the utilization of dense buffering schemes, up to complete replacement of metal wiring with active devices, has been proposed in order to realize efficient and noise-immune clock distribution networks. However, local variance of MOSFET electrical parameters, such as VT and IDSS, increases with scaling of device dimensions, thus causing large intra-die variability of the timing properties of clock buffers. As a consequence, we expect local mismatch to be a significant source of clock skew in deep sub-micron technologies. In order to accurately verify this assumption, we applied advanced statistical simulation techniques and accurate mismatch characterization data to the statistical simulation of relatively small clock distribution networks. The comparison with Monte Carlo simulations performed by neglecting the mismatch effect confirmed that it is necessary to account for local device variations in the design and sizing of the clock distribution network.