Improved FPGA-based dead time compensation for SVM inverters

High performance sensorless AC drives require the exact knowledge of the motor phase voltage in the whole speed range. The use of specific voltage sensors can be avoided if the reference voltage signals can be used instead of the actual (measured) phase voltages. Thus, an accurate compensation of inverter non-idealities is of great interest, and it represents the target of this work. The proposed algorithm overcomes the imprecision of the compensation, which arises in most of the existing methods, caused by an advanced sampling of the phase currents polarity with respect to the switching instants. The implementation of the proposed technique has been made possible solely by the use of an FPGA component, which proves, once more, to be a very attractive co-processor in modern DSP-based digital drives.