The paper demonstrates some techniques for the localization of parasitic paths responsible for the latch-up phenomenon in CMOS integrated circuits, based on voltage contrast or electron beam current induced current (EBIC) in a scanning electron microscope (SEM).

SEM study of latch-up in steady-state and transient conditions

ZANONI, ENRICO
1985

Abstract

The paper demonstrates some techniques for the localization of parasitic paths responsible for the latch-up phenomenon in CMOS integrated circuits, based on voltage contrast or electron beam current induced current (EBIC) in a scanning electron microscope (SEM).
Proceedings of the 15th European Solid State Device Research Conference
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11577/2514413
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