The paper describes techniques for the identification of parasitic paths leading to latch-up in CMOS integrated circuits. Several applications of the "Digital Differential Voltage Contrast" to latch-up studies are presented
CMOS latch-up failure mode analysis
ZANONI, ENRICO;
1986
Abstract
The paper describes techniques for the identification of parasitic paths leading to latch-up in CMOS integrated circuits. Several applications of the "Digital Differential Voltage Contrast" to latch-up studies are presented
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