Correlation between latch-up hysteresis and window effects in commercial CMOS IC's by means of IR microscopy and scanning laser microscopy

The presence of multiple parasitic paths for latch-up triggering in a CMOS integrated circuit gives rise to hysteresis effects in the latch-up I-V characteristics and to "window" effects in the latch-up dynamic threshold. These effects can be explained by identifying active latch-up paths by means of infrared emission microscopy