Electron-beam analysis of the turn-on speed of grounded-gate nMOS ESD protection transistors during Charge-Device-Model (CDM) stress pulses In a highly automated IC production environment, the most relevant ESD hazards are represented by the fast discharge to ground of the charge accumulated on the devices through the manufacturing equipments. This ESD event is described by the Charge Device Model (CDM) and is characterized by very durations and rise-times, in the ns and sub-ns range. The availability of experimental techniques capable of characterizing the response of protection circuits submitted to CDM ESD pulses is of crucial importance to improve IC hardness. This paper shows that an electron beam testing system with 150 ps resolution can provide a detailed information on the dynamic behaviour of grounded gate nMOS transistors submitted to fast, CDM-like tests. These devices protect CMOS ICs' through the action of the lateral npn parasitic transistor associated with the nMOS structure [1]. The measurements demonstrate that the gate length Lg is the most relevant parameter in determining turn-on time of grounded gate nMOS, which is negligibly influenced by drain (source) contact to gate spacings and gate width. The reduced CDM ESD hardness of long Lg transistors has been explained. By exploiting e-beam and capacitance measurements, coupled with a detailed dc characterization of impact-ionization effects, a SPICE model capable of accurately describe device transient behaviour has been derived.

Electron bean analysis of the turn-on speed of grounded-gate nMOS EDS protection transistor during Charged-Device-Model (CDM) stress pulses

MENEGHESSO, GAUDENZIO;
1996

Abstract

Electron-beam analysis of the turn-on speed of grounded-gate nMOS ESD protection transistors during Charge-Device-Model (CDM) stress pulses In a highly automated IC production environment, the most relevant ESD hazards are represented by the fast discharge to ground of the charge accumulated on the devices through the manufacturing equipments. This ESD event is described by the Charge Device Model (CDM) and is characterized by very durations and rise-times, in the ns and sub-ns range. The availability of experimental techniques capable of characterizing the response of protection circuits submitted to CDM ESD pulses is of crucial importance to improve IC hardness. This paper shows that an electron beam testing system with 150 ps resolution can provide a detailed information on the dynamic behaviour of grounded gate nMOS transistors submitted to fast, CDM-like tests. These devices protect CMOS ICs' through the action of the lateral npn parasitic transistor associated with the nMOS structure [1]. The measurements demonstrate that the gate length Lg is the most relevant parameter in determining turn-on time of grounded gate nMOS, which is negligibly influenced by drain (source) contact to gate spacings and gate width. The reduced CDM ESD hardness of long Lg transistors has been explained. By exploiting e-beam and capacitance measurements, coupled with a detailed dc characterization of impact-ionization effects, a SPICE model capable of accurately describe device transient behaviour has been derived.
0871705826
9780871705822
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11577/2522083
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