A silicon-on-insulator (SOI) process for pixelated radiation detectors is developed. It is based on a 0.2 μm CMOS fully depleted (FD-)SOI technology. The SOI wafer is composed of a thick, high-resistivity substrate for the sensing part and a thin Si layer for CMOS circuits. Two types of pixel detectors, one integration-type and the other counting-type, are developed and tested. We confirmed good sensitivity for light, charged particles and X-rays for these detectors. For further improvement on the performance of the pixel detector, we have introduced a new process technique called buried p-well (BPW) to suppress back gate effect. We are also developing vertical (3D) integration technology to achieve much higher density.
Development of SOI pixel process technology
GIUBILATO, PIERO;
2011
Abstract
A silicon-on-insulator (SOI) process for pixelated radiation detectors is developed. It is based on a 0.2 μm CMOS fully depleted (FD-)SOI technology. The SOI wafer is composed of a thick, high-resistivity substrate for the sensing part and a thin Si layer for CMOS circuits. Two types of pixel detectors, one integration-type and the other counting-type, are developed and tested. We confirmed good sensitivity for light, charged particles and X-rays for these detectors. For further improvement on the performance of the pixel detector, we have introduced a new process technique called buried p-well (BPW) to suppress back gate effect. We are also developing vertical (3D) integration technology to achieve much higher density.
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