This study addresses the problem of efficient fault simulation and test generation in circuits using multi-output combinational logic cells. A symbolic fault simulation algorithm is proposed to exploit bit-level parallelism in order to represent the propagation of the output value of faulty cells throughout the circuit, thus accounting for different faulty behaviours in a single simulation step. A satisfiability (SAT)-based test generation procedure is also provided and it early discovers sets of undetectable behaviours. Results for a set of combinational benchmarks show the feasibility of the proposed approach.

Efficient testing of multi-output combinational cells in nano-complementary metal oxide semiconductor integrated circuits

DALPASSO, MARCELLO;
2014

Abstract

This study addresses the problem of efficient fault simulation and test generation in circuits using multi-output combinational logic cells. A symbolic fault simulation algorithm is proposed to exploit bit-level parallelism in order to represent the propagation of the output value of faulty cells throughout the circuit, thus accounting for different faulty behaviours in a single simulation step. A satisfiability (SAT)-based test generation procedure is also provided and it early discovers sets of undetectable behaviours. Results for a set of combinational benchmarks show the feasibility of the proposed approach.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11577/2795692
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