A new experimental technique to evaluate the plasma induced damage at wafer level testing

Plasma processing has become an integral part of the IC fabrication, since it offers advantages in terms of directionality, low temperature and process convenience. However plasma processing induces an oxide charging damage, which is function of process conditions and gate interconnect layout. At the end of the process the plasma damage is "hidden" by hydrogen passivation and becomes latent. At a first electrical inspection all the devices on wafer present nearly the same electrical parameters, whereas a small stress is enough to reveal the plasma damage, producing again a drift of all transistor parameters. In fact the applied stress both depassivate the latent plasma damage and introduce newly defects, which are electrically undistinguishable from plasma damage and depend on applied stress conditions. In our contribution we propose an experimental stress methodology to investigate both the latent damage depassivation effect and the net contribution of plasma damage.