This work presents a hardware and software architecture which can be used in those systems that implement practical Quantum Key Distribution (QKD) and Quantum Random Number Generation (QRNG) schemes. This architecture fully exploits the capability of a System-on-a-Chip (SoC) which comprehends both a Field Programmable Gate Array (FPGA) and a dual core CPU unit. By assigning the time-related tasks to the FPGA and the management to the CPU, we built a flexible system with optimized resource sharing on a commercial off-the-shelf (COTS) evaluation board which includes a SoC. Furthermore, by changing the dataflow direction, the versatile system architecture can be exploited as a QKD transmitter, QKD receiver and QRNG control-acquiring unit. Finally, we exploited the dual core functionality and realized a concurrent stream device to implement a practical QKD transmitter where one core continuously receives fresh data at a sustained rate from an external QRNG source while the other operates with the FPGA to drive the qubits transmission to the QKD receiver. The system was successfully tested on a long-term run proving its stability and security. This demonstration paves the way towards a more secure QKD implementation, with fully unconditional security as the QKD states are entirely generated by a true random process and not by deterministic expansion algorithms. Eventually, this enables the realization of a standalone quantum transmitter, including both the random numbers and the qubits generation.

Versatile and concurrent FPGA-based architecture for practical quantum communication systems

Stanco A.;Santagiustina F. B. L.;Calderaro L.;Avesani M.;Bertapelle T.;Dequal D.;Vallone G.;Villoresi P.
2022

Abstract

This work presents a hardware and software architecture which can be used in those systems that implement practical Quantum Key Distribution (QKD) and Quantum Random Number Generation (QRNG) schemes. This architecture fully exploits the capability of a System-on-a-Chip (SoC) which comprehends both a Field Programmable Gate Array (FPGA) and a dual core CPU unit. By assigning the time-related tasks to the FPGA and the management to the CPU, we built a flexible system with optimized resource sharing on a commercial off-the-shelf (COTS) evaluation board which includes a SoC. Furthermore, by changing the dataflow direction, the versatile system architecture can be exploited as a QKD transmitter, QKD receiver and QRNG control-acquiring unit. Finally, we exploited the dual core functionality and realized a concurrent stream device to implement a practical QKD transmitter where one core continuously receives fresh data at a sustained rate from an external QRNG source while the other operates with the FPGA to drive the qubits transmission to the QKD receiver. The system was successfully tested on a long-term run proving its stability and security. This demonstration paves the way towards a more secure QKD implementation, with fully unconditional security as the QKD states are entirely generated by a true random process and not by deterministic expansion algorithms. Eventually, this enables the realization of a standalone quantum transmitter, including both the random numbers and the qubits generation.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11577/3416947
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