This article addresses high-frequency admittance modeling of current-controlled voltage source converters (VSCs). Recent studies have shown that harmonic instability may also occur at frequencies above the Nyquist frequency. To form an accurate multiple-frequency model in this frequency range, sidebands that originate from modulation and sampling must be examined. In this article, an accurate small-signal model is developed taking into account an adequate digital pulsewidth modulator (DPWM) representation, which allows to predict dependence of the frequency response on the steady-state dc (SS-dc) operating point. It is shown that when center-pulse sampling is implemented, pulsewidth modulation sidebands do not create additional loops leaving only sampling sidebands to be considered. Using the same approach as for SS-dc operation, a model that accurately represents admittance measurements during sinusoidal ac (S-ac) operation is developed. Its basis is a novel DPWM model suitable for S-ac regime, which allows to predict dependence of the VSC’s input admittance on the grid voltage magnitude. Experimental and simulated admittance measurements, performed on a single-phase two-level VSC during various SS-dc and S-ac regimes, match with the proposed models up to twice the sampling frequency.

Accurate High-Frequency Modeling of the Input Admittance of PWM Grid-Connected VSCs

Cvetanovic R.
Investigation
;
Mattavelli P.
Supervision
;
Buso S.
Supervision
2022

Abstract

This article addresses high-frequency admittance modeling of current-controlled voltage source converters (VSCs). Recent studies have shown that harmonic instability may also occur at frequencies above the Nyquist frequency. To form an accurate multiple-frequency model in this frequency range, sidebands that originate from modulation and sampling must be examined. In this article, an accurate small-signal model is developed taking into account an adequate digital pulsewidth modulator (DPWM) representation, which allows to predict dependence of the frequency response on the steady-state dc (SS-dc) operating point. It is shown that when center-pulse sampling is implemented, pulsewidth modulation sidebands do not create additional loops leaving only sampling sidebands to be considered. Using the same approach as for SS-dc operation, a model that accurately represents admittance measurements during sinusoidal ac (S-ac) operation is developed. Its basis is a novel DPWM model suitable for S-ac regime, which allows to predict dependence of the VSC’s input admittance on the grid voltage magnitude. Experimental and simulated admittance measurements, performed on a single-phase two-level VSC during various SS-dc and S-ac regimes, match with the proposed models up to twice the sampling frequency.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11577/3458096
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