Thermomechanical Stresses in Silicon Chips for Optoelectronic Devices

The growing interest in improving optoelectronic devices requires continuous research of the materials and processes involved in manufacturing. From a chemical point of view, the study of this sector is crucial to optimize existing manufacturing processes or create new ones. This work focusses on the experimental evaluation of residual stresses on samples that are intended to simulate part of the structure of an optoelectronic device. It represents an important starting point for the development of optoelectronic devices with characteristics suitable for future industrial production. Silicon chips, with a thickness of 120 mu m, were soldered onto copper and alumina substrates, using different assembly parameters in terms of temperature and pressure. Using Raman spectroscopy, the stress evaluation was estimated in a wide temperature range, from -50 to 180 degrees C. Silicon chips soldered with AuSn alloy on copper substrates demonstrated at 22 degrees C a compressive stress, developed in the center of the assembly with a maximum value of -600 MPa, which reached -1 GPa at low temperatures. They present a stress distribution with a symmetric profile with respect to the central area of the chip. The silicon chip assembled on a ceramic substrate without pressure turned out to be extremely interesting. Even in the absence of pressure, the sample did not show a large shift in the Raman position, indicating a low stress.