Efficiency Optimization of Voltage-Mode CMOS Digital Doherty Power Amplifiers

This article analyzes the behavior of a single supply asymmetric Doherty power amplifier, made of two switched-capacitor power amplifiers (SCPAs) and a power combining network. The proposed analysis shows that there is an optimal power partition between the two SCPAs that maximizes the efficiency at each output power level. The optimal control of the PA leads to two power back-off (PBO) efficiency peaks, whose magnitude depends on the size of the switches of each SCPA and on the matching network design. The optimization of both switch sizing and output network design is carried out analytically. The achieved theoretical results are then verified by transistor-level simulations. They have also been validated by measurements performed on a prototype, fully integrated in a commercial 22-nm CMOS technology, at an operation frequency of 2.3 GHz.