This work proposes a ΣΔ converter for a multistandard wireless receiver. The modulator is based on a cascaded 2-1-1 architecture that allows to switch on and off the cascaded stages. As a result a wide range of programmability for the modulator is achieved and the converter can match all the requirements for GSM, UMTS and WLANa standards. Circuit feasibility of the converter has been proved by the design of the required amplifiers in a 0.35μm CMOS technology, while a behavioural model that includes all main sources of error demonstrates the correct performance of the converter with respect to all the three mentioned standards.

A Programmable-Order Sigma-Delta Converter for a Multi-Standard Wireless Receiver

XOTTA, ANDREA GIOVANNI;GEROSA, ANDREA;NEVIANI, ANDREA
2004

Abstract

This work proposes a ΣΔ converter for a multistandard wireless receiver. The modulator is based on a cascaded 2-1-1 architecture that allows to switch on and off the cascaded stages. As a result a wide range of programmability for the modulator is achieved and the converter can match all the requirements for GSM, UMTS and WLANa standards. Circuit feasibility of the converter has been proved by the design of the required amplifiers in a 0.35μm CMOS technology, while a behavioural model that includes all main sources of error demonstrates the correct performance of the converter with respect to all the three mentioned standards.
Proceedings of the Workshop on Wireless Circuits and Systems
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11577/1349241
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