Alternative ESD Protection Structure in CMOS Technology for the Manufacture of High-Density Integration Circuits

The aim of this paper is to show an alternative protection structure that occupy less space with respect traditional SCR, but have the same robustness. Besides, this new structure present two different holding voltage: one low (about 2V) during an ESD event and the other high (about 7V or more) during normal operation condition of the circuit that must be protected. This two aspects are essential, in fact the first allows to overcame one of the greater problem of a protection structure that, in order to carry big currents, presents a bulky dimensions. The second allows to have a low power dissipation during ESD events and, contemporary, to avoid latch-up conditions during the normal operation. Furthermore such flexibility allows to adapt the same protection device to many different technologies in an easy way. In fact, the same protection structure can be used for many different supply voltages without changing any layout parameter.