In this paper, the design of a fully analog iterative decoder for a serially concatenated convolutional code is presented. The decoder is reconfigurable in both block length and code rate. An interleaver size up to 2400 bit is considered. The decoder core implements a single SISO working on a window of the whole code trellis. It is then reused several times to decode the two constituent codes. The resulting decoder performs iterations, but it is fully analog. The extrinsic information exchanged in the decoding process is stored in an analog memory and permuted through a reconfigurable interleaver. Behavioral analysis of the decoder as well as precision and mismatch impact on performance are reported in the paper.

Reconfigurable Analog Decoder for a Serially Concatenated Convolutional Code

VOGRIG, DANIELE;NEVIANI, ANDREA;GEROSA, ANDREA
2006

Abstract

In this paper, the design of a fully analog iterative decoder for a serially concatenated convolutional code is presented. The decoder is reconfigurable in both block length and code rate. An interleaver size up to 2400 bit is considered. The decoder core implements a single SISO working on a window of the whole code trellis. It is then reused several times to decode the two constituent codes. The resulting decoder performs iterations, but it is fully analog. The extrinsic information exchanged in the decoding process is stored in an analog memory and permuted through a reconfigurable interleaver. Behavioral analysis of the decoder as well as precision and mismatch impact on performance are reported in the paper.
Proceedings of IEEE Global Telecommunications Conference, 2006.
9781424403561
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11577/2433584
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