The design and test results of a three-metal, double-poly, 0.35 μm; CMOS analog turbo decoder for the rate-1/3, block length 40, UMTS turbo code, are presented. A discrete-time model of analog decoding networks is also presented. This model can be used as a tool to both predict chip performance in a short time and give design guidelines for complex decoders, for which circuit-level simulations are impractical.

An analog turbo decoder for the UMTS standard

VOGRIG, DANIELE;NEVIANI, ANDREA;GEROSA, ANDREA
2004

Abstract

The design and test results of a three-metal, double-poly, 0.35 μm; CMOS analog turbo decoder for the rate-1/3, block length 40, UMTS turbo code, are presented. A discrete-time model of analog decoding networks is also presented. This model can be used as a tool to both predict chip performance in a short time and give design guidelines for complex decoders, for which circuit-level simulations are impractical.
Proceedings. International Symposium on Information Theory, 2004.
9780780382800
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11577/2440743
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