ESD robustness of smart-power protection structures evaluated by means of HBM and TLP tests

In this paper we will present data concerning the ESD robustness of smart power protection structures (fabricated in Bipolar, CMOS, DMOS, BCD technology) for input-output circuits. A comparison between the robustness of “p-body” and “p-well” based structures and a study of the influence of layout parameters on the ESD robustness will be given. The correlation between ESD robustness obtained with different test methods (HBM and TLP) will be also presented. Failure analysis has been carried out by means of SEM device cross-sections