This work proposes an architecture for a multimode ADC. The architecture is based on the cascade of a single-bit 2-1 SigmaDelta modulator and a 4-bit flash converter. Furthermore such an architecture is mapped in a modular implementation, which allows to easily reconfigure modulator order, oversampling ratio and equivalent number of bits of the internal quantizer. As a consequence the proposed converter can fulfil the requirement of a wide range of standards: GSM, Bluetooth, UMTS and WLANa. The achieved dynamic range is 85dB, 72dB, 62dB and 59dB for GSM, Bluetooth, UMTS and WLANa, respectively. The corresponding power consumption is 4.6mW, 5.5mW, 7.4mW and 18.9mW

An optimal architecture for a multimode ADC, based on the cascade of a Sigma/Delta modulator and a flash converter

GEROSA, ANDREA;BEVILACQUA, ANDREA;NEVIANI, ANDREA;XOTTA, ANDREA GIOVANNI
2006

Abstract

This work proposes an architecture for a multimode ADC. The architecture is based on the cascade of a single-bit 2-1 SigmaDelta modulator and a 4-bit flash converter. Furthermore such an architecture is mapped in a modular implementation, which allows to easily reconfigure modulator order, oversampling ratio and equivalent number of bits of the internal quantizer. As a consequence the proposed converter can fulfil the requirement of a wide range of standards: GSM, Bluetooth, UMTS and WLANa. The achieved dynamic range is 85dB, 72dB, 62dB and 59dB for GSM, Bluetooth, UMTS and WLANa, respectively. The corresponding power consumption is 4.6mW, 5.5mW, 7.4mW and 18.9mW
Proceedings of 2006 IEEE International Symposium on Circuits and Systems, ISCAS 2006
9780780393899
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11577/2463580
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