Techniques For Latch-up Analysis In CMOS ICs Based On Scanning Electron-microscopy

Scanningelectronmicroscopytechniques for the characterization of latch-up phenomena in CMOS integrated circuits are reported, critically rewieved and compared with experimental techniques described in the literature, based on infra-red and scanning laser microscopy. Several examples of application are presented to demonstrate the capability of a SEM system for practical layout debugging. Described SEM techniques comprise: (a) sensitivity analysis by means of ebeam induced current, with digital control of the beam position and beam blanking to avoid MOS damaging; (b) identification of latch-up sites in steady-state by Digital Differential Voltage Contrast; (c) study of transient and triggering phenomena and localization of latch-up firing points by means of stroboscopic voltage contrast.