One of the most hazardous reliability problems for CMOS IC's is due to the latch-up failure mechanism, which consists in the turning on of a parasitic SCR (Semiconductor Controlled Rectifier), with consequent short circuit of the Vdd and Vss lines and device destruction. This paper reports, critically reviews, and compares experimental techniques for localization and sensitivity analysis of latch-up. Described techniques include: IR thermography, IR emission microscopy, SEM capacitively-coupled voltage contrast and stroboscopic techniques, sensitivity analysis by means of e beam and laser-induced current. To make an easier comparison, most of the techniques are discussed referring to their application to the same CMOS structure.
Analytical techniques for localization and sensitivity analysis of latch-up in CMOS IC's
ZANONI, ENRICO;
1989
Abstract
One of the most hazardous reliability problems for CMOS IC's is due to the latch-up failure mechanism, which consists in the turning on of a parasitic SCR (Semiconductor Controlled Rectifier), with consequent short circuit of the Vdd and Vss lines and device destruction. This paper reports, critically reviews, and compares experimental techniques for localization and sensitivity analysis of latch-up. Described techniques include: IR thermography, IR emission microscopy, SEM capacitively-coupled voltage contrast and stroboscopic techniques, sensitivity analysis by means of e beam and laser-induced current. To make an easier comparison, most of the techniques are discussed referring to their application to the same CMOS structure.Pubblicazioni consigliate
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