Transiently triggered latch-up in CMOS twin-tub and epitaxial technologies

We present in this work an analysis of transiently triggered latch-up in test-structures fabricated using a twin-tub process implemented on two different substrates: a p-type and a p p+ epitaxial one. Steady-state electrical characterization confirmed the well-known increased latch-up resistance of epitaxial structures with respect to standard ones. In this paper it is shown that, depending on the chosen electrical configuration, when latch-up is transiently triggered, epitaxial structures may have dynamic triggering currents lower than twin-tub ones. The influence of some layout variables on turn-on threshold voltage has been investigated for all samples.