Analysis of ESD protection networks for DMOS power transistors by means of static and time-resolved emission microscopy

Different ESD input/output protection networks, based on Zener diodes and lateral npn transistors have been implemented with the aim of characterizing their effectiveness in protecting vertical DMOS power transistors. Failure mechanisms have been identified by means of static emission microscopy. Gated emission microscopy, in synchronism with a voltage pulse emulating the ESD event, enables the dynamic behaviour of protection structures to be analysed, identifying lateral current crowding effects which explain the observed failure mechanisms.