Understanding the potential and the limits of Germanium pMOSFETs for VLSI circuits from experimental measurements

In this paper, potential and limits of Germanium pMOSFETs for VLSI applications are investigated from a circuit perspective for the first time in the literature. Since short-channel Germanium devices have been developed only recently, no circuit design tools are currently available, hence most of the results available in the literature address process and device-level issues (currently, down to the 65 nm node). However, the suitability of Germanium MOSFETs for VLSI circuits should be assessed at circuit level. To fill this gap, we introduce an innovative methodology that extracts the main circuit parameters of interest (e. g., speed, dynamic power, leakage) from measurements on experimental devices. Appropriate figures of merit are adopted to highlight the potential of Germanium MOSFETs under realistic VLSI designs that fully exploit system-level schemes to minimize leakage (e. g., body biasing, stack forcing, power gating). Measurements and evaluations are performed on 125 nm Germanium pMOSFETs with a high-kappa/metal gate stack having an equivalent oxide thickness of 1.3 nm. Comparison with Si pMOSFET prototypes implemented with similar gate stack is also carried out to comparatively understand the potential and the weaknesses of Germanium transistors. The main experimental results are justified through theoretical analysis as a function of the relevant circuit and device parameters. Some system-level aspects are also investigated, such as the energy efficiency and the wakeup time of body-biasing schemes in Ge circuits and the impact of voltage scaling.