Ionizing radiation may affect the electrical response of the electronic systems, inducing a variation in their nominal electrical characteristics and gradually degrading their performance. It is essential to study the total ionizing dose (TID) effects in electronic devices used in radiation environments such as space and avionics systems, high-energy physics experiments, and nuclear power plants. This thesis mainly focuses on the high-energy experiments, in which the large hadron collider (LHC) at CERN, especially the upgraded high luminosity-LHC, is currently expected to reach the highest TID level. In this thesis work, I investigate the TID effects in nanometer scale CMOS technologies irradiated to ultra-high doses. The analysis of TID degradation mechanisms focuses on evaluating the measurable effects that affect the electrical characteristics of the devices and identifying the microscopic properties of the radiation-induced defects. The radiation measurements of several transistors based on the FinFET and gate-all-around FET (GAAFET) structures of different manufactures are performed with different device types, dimensions, chip layout and bias conditions, identifying the most TID sensitive parameters of the devices. The type, density, location and energy levels of the defects induced by ionizing radiation are studied through DC static characteristics and low-frequency 1/f noise measurements. The experimental measurements presented in this work provide a unique and comprehensive set of data, pointing out the strong effect of scaling down on the TID-induce phenomena in modern advanced CMOS technologies. All TID responses of the 16 nm bulk FinFETs and Si nanowire GAAFETs confirm the high TID tolerance of the nanoscale CMOS technologies with ultra-thin gate oxide, due to the reduced charge trapping in the gate dielectrics. However, the aggressive scale down of devices has led to new TID-induced effects related to other thick oxides and modern fabrication processes, such as shallow trench insulation (STI) oxides, spacer dielectrics, and halo implantations. Some new TID degradation mechanisms appear in 16 nm bulk FinFETs and Si nanowire GAAFETs, causing strong dependence on the irradiation bias conditions, channel length and chip layout. This thesis work identifies the weak points of FinFET and GAAFET technologies at ultra-high doses and provides chip designers with the key elements to improve their TID tolerance.

Ionizing radiation may affect the electrical response of the electronic systems, inducing a variation in their nominal electrical characteristics and gradually degrading their performance. It is essential to study the total ionizing dose (TID) effects in electronic devices used in radiation environments such as space and avionics systems, high-energy physics experiments, and nuclear power plants. This thesis mainly focuses on the high-energy experiments, in which the large hadron collider (LHC) at CERN, especially the upgraded high luminosity-LHC, is currently expected to reach the highest TID level. In this thesis work, I investigate the TID effects in nanometer scale CMOS technologies irradiated to ultra-high doses. The analysis of TID degradation mechanisms focuses on evaluating the measurable effects that affect the electrical characteristics of the devices and identifying the microscopic properties of the radiation-induced defects. The radiation measurements of several transistors based on the FinFET and gate-all-around FET (GAAFET) structures of different manufactures are performed with different device types, dimensions, chip layout and bias conditions, identifying the most TID sensitive parameters of the devices. The type, density, location and energy levels of the defects induced by ionizing radiation are studied through DC static characteristics and low-frequency 1/f noise measurements. The experimental measurements presented in this work provide a unique and comprehensive set of data, pointing out the strong effect of scaling down on the TID-induce phenomena in modern advanced CMOS technologies. All TID responses of the 16 nm bulk FinFETs and Si nanowire GAAFETs confirm the high TID tolerance of the nanoscale CMOS technologies with ultra-thin gate oxide, due to the reduced charge trapping in the gate dielectrics. However, the aggressive scale down of devices has led to new TID-induced effects related to other thick oxides and modern fabrication processes, such as shallow trench insulation (STI) oxides, spacer dielectrics, and halo implantations. Some new TID degradation mechanisms appear in 16 nm bulk FinFETs and Si nanowire GAAFETs, causing strong dependence on the irradiation bias conditions, channel length and chip layout. This thesis work identifies the weak points of FinFET and GAAFET technologies at ultra-high doses and provides chip designers with the key elements to improve their TID tolerance.

Effetti da Radiazione Ionizzante a Dosi Ultra Alte in Tecnologie CMOS su Scala Nanometrica / Ma, Teng. - (2022 Mar 08).

Effetti da Radiazione Ionizzante a Dosi Ultra Alte in Tecnologie CMOS su Scala Nanometrica

MA, TENG
2022

Abstract

Ionizing radiation may affect the electrical response of the electronic systems, inducing a variation in their nominal electrical characteristics and gradually degrading their performance. It is essential to study the total ionizing dose (TID) effects in electronic devices used in radiation environments such as space and avionics systems, high-energy physics experiments, and nuclear power plants. This thesis mainly focuses on the high-energy experiments, in which the large hadron collider (LHC) at CERN, especially the upgraded high luminosity-LHC, is currently expected to reach the highest TID level. In this thesis work, I investigate the TID effects in nanometer scale CMOS technologies irradiated to ultra-high doses. The analysis of TID degradation mechanisms focuses on evaluating the measurable effects that affect the electrical characteristics of the devices and identifying the microscopic properties of the radiation-induced defects. The radiation measurements of several transistors based on the FinFET and gate-all-around FET (GAAFET) structures of different manufactures are performed with different device types, dimensions, chip layout and bias conditions, identifying the most TID sensitive parameters of the devices. The type, density, location and energy levels of the defects induced by ionizing radiation are studied through DC static characteristics and low-frequency 1/f noise measurements. The experimental measurements presented in this work provide a unique and comprehensive set of data, pointing out the strong effect of scaling down on the TID-induce phenomena in modern advanced CMOS technologies. All TID responses of the 16 nm bulk FinFETs and Si nanowire GAAFETs confirm the high TID tolerance of the nanoscale CMOS technologies with ultra-thin gate oxide, due to the reduced charge trapping in the gate dielectrics. However, the aggressive scale down of devices has led to new TID-induced effects related to other thick oxides and modern fabrication processes, such as shallow trench insulation (STI) oxides, spacer dielectrics, and halo implantations. Some new TID degradation mechanisms appear in 16 nm bulk FinFETs and Si nanowire GAAFETs, causing strong dependence on the irradiation bias conditions, channel length and chip layout. This thesis work identifies the weak points of FinFET and GAAFET technologies at ultra-high doses and provides chip designers with the key elements to improve their TID tolerance.
Total Ionizing Dose Effects in Nanometer Scale CMOS Technologies Irradiated to Ultra-High Doses
8-mar-2022
Ionizing radiation may affect the electrical response of the electronic systems, inducing a variation in their nominal electrical characteristics and gradually degrading their performance. It is essential to study the total ionizing dose (TID) effects in electronic devices used in radiation environments such as space and avionics systems, high-energy physics experiments, and nuclear power plants. This thesis mainly focuses on the high-energy experiments, in which the large hadron collider (LHC) at CERN, especially the upgraded high luminosity-LHC, is currently expected to reach the highest TID level. In this thesis work, I investigate the TID effects in nanometer scale CMOS technologies irradiated to ultra-high doses. The analysis of TID degradation mechanisms focuses on evaluating the measurable effects that affect the electrical characteristics of the devices and identifying the microscopic properties of the radiation-induced defects. The radiation measurements of several transistors based on the FinFET and gate-all-around FET (GAAFET) structures of different manufactures are performed with different device types, dimensions, chip layout and bias conditions, identifying the most TID sensitive parameters of the devices. The type, density, location and energy levels of the defects induced by ionizing radiation are studied through DC static characteristics and low-frequency 1/f noise measurements. The experimental measurements presented in this work provide a unique and comprehensive set of data, pointing out the strong effect of scaling down on the TID-induce phenomena in modern advanced CMOS technologies. All TID responses of the 16 nm bulk FinFETs and Si nanowire GAAFETs confirm the high TID tolerance of the nanoscale CMOS technologies with ultra-thin gate oxide, due to the reduced charge trapping in the gate dielectrics. However, the aggressive scale down of devices has led to new TID-induced effects related to other thick oxides and modern fabrication processes, such as shallow trench insulation (STI) oxides, spacer dielectrics, and halo implantations. Some new TID degradation mechanisms appear in 16 nm bulk FinFETs and Si nanowire GAAFETs, causing strong dependence on the irradiation bias conditions, channel length and chip layout. This thesis work identifies the weak points of FinFET and GAAFET technologies at ultra-high doses and provides chip designers with the key elements to improve their TID tolerance.
Effetti da Radiazione Ionizzante a Dosi Ultra Alte in Tecnologie CMOS su Scala Nanometrica / Ma, Teng. - (2022 Mar 08).
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11577/3439939
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