Different phase-locked loop algorithms applied to three-phase grid voltages implement a closed control loop based on the Park transform to obtain the grid voltage instantaneous phase and frequency. When a single-phase grid voltage must be processed, one of the inputs of the Park transform is generated by a block that, starting from the available voltage, computes an additional signal with the same frequency of the grid voltage and ideally orthogonal to it. This paper introduces a novel method for the orthogonal signal generation and gives a detailed analysis of its functioning. Then, after sizing the control loop of the phase-locked loop, the paper considers different aspects relevant to implementation of the presented orthogonal signal generation and of the phase-locked loop on a digital signal controller, such as the finite numerical resolution, the memory usage and the computation time. Finally, the paper checks the comprehensive performance of the orthogonal signal generation and phase-locked loop pair by experimental tests and compares the obtained results with those available in the literature.

Design and Experimentation of a Single-Phase PLL With Novel OSG Method

Bertoluzzo, M
Membro del Collaboration Group
;
Giacomuzzi, S
Membro del Collaboration Group
;
Kumar, A
Membro del Collaboration Group
2022

Abstract

Different phase-locked loop algorithms applied to three-phase grid voltages implement a closed control loop based on the Park transform to obtain the grid voltage instantaneous phase and frequency. When a single-phase grid voltage must be processed, one of the inputs of the Park transform is generated by a block that, starting from the available voltage, computes an additional signal with the same frequency of the grid voltage and ideally orthogonal to it. This paper introduces a novel method for the orthogonal signal generation and gives a detailed analysis of its functioning. Then, after sizing the control loop of the phase-locked loop, the paper considers different aspects relevant to implementation of the presented orthogonal signal generation and of the phase-locked loop on a digital signal controller, such as the finite numerical resolution, the memory usage and the computation time. Finally, the paper checks the comprehensive performance of the orthogonal signal generation and phase-locked loop pair by experimental tests and compares the obtained results with those available in the literature.
2022
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11577/3442222
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