Hot-carrier degradation and oxide charge build-up in self-aligned etched-polysilicon npn bipolar transistors

The aim of this work is to present the results of several accelerated tests performed on self-aligned, etchedpolysilicon, npn bipolar transistors with silicon dioxide emitter spacers, and to propose a new technique for the characterization of the electric field at the periphery (that is, at the interface between silicon and the silicon dioxide spacer) of the base-emitter junction. Tests are performed reverse-biasing at constant current the base-emitter junction (with floating collector) both in the tunneling and avalanche regime. The results are found to be in good agreement with existing degradation models, and show that degradation kinetics may depend to some extent on device layout, particularly in avalanche regime. The influence of charge injection in the oxide on degradation kinetics is also analyzed and compared to the predictions of an existing model. To this aim, a new method for estimating charge injection in the oxide is proposed; the method consists in evaluating the decrease of the electric field at the periphery of the device by measuring the temperature dependence of the tunneling component of reverse base current. The electric field behavior is then compared to the degradation dependence on stress time in the different stress regimes.