We present new experimental results on heavy ion-induced gate rupture on deep submicron CMOS transistor arrays. Through the use of dedicated test structures, composed by a large number of 130-nm MOSFETs connected in parallel, we show the response to heavy ion irradiation under high stress voltages of devices previously irradiated with X-rays. We found only a slight impact on gate rupture critical voltage at a LET of 32 MeV cm(2) mg(-1) for devices previously irradiated up to 3 Mrad(SiO(2)), and practically no change for 100 Mrad(SiO(2)) irradiation, dose of interest for the future super large hadron collider (SLHC).

Single Event Gate Rupture in 130-nm CMOS Transistor Arrays Subjected to X-Ray Irradiation

SILVESTRI, MARCO;GERARDIN, SIMONE;PACCAGNELLA, ALESSANDRO
2010

Abstract

We present new experimental results on heavy ion-induced gate rupture on deep submicron CMOS transistor arrays. Through the use of dedicated test structures, composed by a large number of 130-nm MOSFETs connected in parallel, we show the response to heavy ion irradiation under high stress voltages of devices previously irradiated with X-rays. We found only a slight impact on gate rupture critical voltage at a LET of 32 MeV cm(2) mg(-1) for devices previously irradiated up to 3 Mrad(SiO(2)), and practically no change for 100 Mrad(SiO(2)) irradiation, dose of interest for the future super large hadron collider (SLHC).
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Utilizza questo identificativo per citare o creare un link a questo documento: http://hdl.handle.net/11577/2426474
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