Growth morphologies and electrical properties of pentacene organic TFT with SiO2/parylene dielectric layer

The growth control of pentacene thin layer on parylene/SiO2/Si substrates is investigated by focusing on their structure and electrical properties. Different 40-nm pentacene thin layers were grown, by changing the substrate temperature in the range of 30 – 90°C, at constant evaporation flux rate. The various layer show different surface morphology and grain structures. The surface morphology was investigated using atomic force microscopy (AFM) and, for revealing the pentacene phases in the structures, by micro-Raman spectroscopy. The electrical measurements results show that the morphology, crystal structure and molecular ordering of the pentacene layers have a strong impact on carrier transport phenomena and they can be correlated with the results obtained by AFM and micro -Raman analysis, where the optimal substrate temperature 50 °C was determined. The additional parylene dielectric layer brings benefits by strongly reducing the charge rapping/detrapping centres formed at pentacene-parylene interface, which was approved by C-V measurements.