Optimization of ESD protection structures suitable for BCD6 smart power technology

In this work we present results concerning the optimization of BCD6 ESD protection structures based on the lateral DMOS transistor to be used in ESD protection structures adopting the “Big-Clamp” approach. The influence of common lines parasitic resistance on ESD robustness has been characterized, both by means of TLP measurements and HBM testing. Threshold voltage shift in NMOS input buffer transistor, following HBM test, has been detected, suggesting a new failure criteria that should be taken into account for these protection structures. Simple gate-coupled LDMOS devices with different N-well doping has also been investigated with the aim to identify the effect of the well doping on the ESD robustness.