Impact of unrealistic worst case modeling on the performance of VLSI circuits in deep submicron CMOS technologies

The impact of process fluctuations on the variability of deep submicron (DSM) very large scale integration (VLSI) circuit performances is investigated in this paper. In particular, we show that as process dimensions scale down in the subhalfmicron region, the relative weight of process variability tends to increase, thus wearing down a non negligible portion of the benefits that are expected from minimum feature size scaling. We will show that in order to better exploit the advance of process technology, it is essential to adopt a realistic approach to worst case modeling, as the one described in [1] [assigned probability technique (APT)]. The application of the APT technique to different test circuits designed in 0.35, 0.25, and 0.18 m CMOS technologies with a power supply ranging from 3.3 V down to 1 V will demonstrate how the manufacturability of DSM designs is going to be a vital factor for the successful implementation of high-performance or low-power systems in 0.18 m and lesser technologies.