– Two-dimensional device simulations are adopted as a tool to characterize deep levels in 6H-SiC, buried gate, n-channel JFETs. Deep levels can be detected by means of Deep Level Transient Spectroscopy (DLTS) or transconductance frequency dispersion measurements. Subsequent simulation of the drain-current transients following the application of a gate-source voltage step allows the energetic and spatial position of the different deep levels to be inferred.
Deep-Level Characterization in 6H-SiC JFETs by Means of Two-Dimensional Device Simulations
MENEGHESSO, GAUDENZIO;CHINI, ALESSANDRO;ZANONI, ENRICO
2002
Abstract
– Two-dimensional device simulations are adopted as a tool to characterize deep levels in 6H-SiC, buried gate, n-channel JFETs. Deep levels can be detected by means of Deep Level Transient Spectroscopy (DLTS) or transconductance frequency dispersion measurements. Subsequent simulation of the drain-current transients following the application of a gate-source voltage step allows the energetic and spatial position of the different deep levels to be inferred.File in questo prodotto:
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