The potential performances and limitations of an all-analogue implementation of a posteriori-probability (APP) decoders in a standard complementary-metal-oxide semiconductor (CMOS) technology are investigated. In particular, the accuracy and speed trade-off related to the usage of MOS transistors in the weak inversion (w.i) region is analysed in depth. Transistor level simulations of a (18, 9, 5) tail-biting decoder are reported and contrasted with the results of the software implementation of the same decoding algorithm

CMOS implementation of all-analogue APP decoders: analysis of performances and limitations

GEROSA, ANDREA;NEVIANI, ANDREA
2001

Abstract

The potential performances and limitations of an all-analogue implementation of a posteriori-probability (APP) decoders in a standard complementary-metal-oxide semiconductor (CMOS) technology are investigated. In particular, the accuracy and speed trade-off related to the usage of MOS transistors in the weak inversion (w.i) region is analysed in depth. Transistor level simulations of a (18, 9, 5) tail-biting decoder are reported and contrasted with the results of the software implementation of the same decoding algorithm
2001
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11577/2465446
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