Total-ionizing-dose (TID) mechanisms are evaluated in 16 nm Si bulk FinFETs at doses up to 1 Grad(SiO2) for applications in high-energy physics experiments. The TID effects are evaluated through DC and low-frequency noise measurements by varying irradiation bias conditions, transistor channel lengths, and fin/finger layouts. The TID response of nFinFETs irradiated under positive gate bias at ultrahigh doses shows a rebound of threshold voltage with significant increase in the 1/f noise amplitude. The degradation is related to the generation of border and interface traps at the upper corners of STI oxides and at the gate oxide/channel interfaces. In contrast, pFinFETs have the worst degradation due to positive charge trapping in STI oxides, which severely degrades the device transconductance and total drain current, while negligible effects are visible in the threshold voltage and 1/f noise. The TID sensitivity depends strongly on the transistor layout. Short-channel devices have the best TID tolerance thanks to the influence of halo implantations, while pFinFETs designed with low number of fins have the worst degradation because of high densities of positive charge in the surrounding thick STI oxides. As a guideline for IC design, short-channel transistors with more than 4-fins may be preferred in order to facilitate circuit qualification.

DC response, low-frequency noise, and TID-induced mechanisms in 16-nm FinFETs for high-energy physics experiments

Bonaldo S.;Ma T.;Mattiazzo S.;Paccagnella A.;Gerardin S.
2022

Abstract

Total-ionizing-dose (TID) mechanisms are evaluated in 16 nm Si bulk FinFETs at doses up to 1 Grad(SiO2) for applications in high-energy physics experiments. The TID effects are evaluated through DC and low-frequency noise measurements by varying irradiation bias conditions, transistor channel lengths, and fin/finger layouts. The TID response of nFinFETs irradiated under positive gate bias at ultrahigh doses shows a rebound of threshold voltage with significant increase in the 1/f noise amplitude. The degradation is related to the generation of border and interface traps at the upper corners of STI oxides and at the gate oxide/channel interfaces. In contrast, pFinFETs have the worst degradation due to positive charge trapping in STI oxides, which severely degrades the device transconductance and total drain current, while negligible effects are visible in the threshold voltage and 1/f noise. The TID sensitivity depends strongly on the transistor layout. Short-channel devices have the best TID tolerance thanks to the influence of halo implantations, while pFinFETs designed with low number of fins have the worst degradation because of high densities of positive charge in the surrounding thick STI oxides. As a guideline for IC design, short-channel transistors with more than 4-fins may be preferred in order to facilitate circuit qualification.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11577/3450089
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