TID effects in the lateral STI oxide of planar CMOS transistors

Using comprehensive experimental data and 3D Technology Computer-Aided Design simulations, this paper discusses the effects and mechanisms of Total Ionizing Dose (TID) in the lateral Shallow Trench Isolation (STI) in planar CMOS technologies in the 65-28 nm nodes. During irradiation to ultra-high doses, nMOS transistors often exhibit a continuous increase in the off-state (leakage) current, while the evolution of the on-current, threshold voltage, and transconductance show a rebound that is considerably more evident in narrow channel transistors. This difference in the on- and off-state parameters evolution with TID is traceable to variable de-passivation of interface traps in depth along the STI sidewall. While at all depths TID determines a build-up of trapped holes in the STI oxide, only in the shallower portion a significant number of interface traps are gradually de-passivated leading to an accumulation of negative trapped charge. The different dynamics of hole and electron trapping determines the rebound of the on-state parameters in typical high-dose-rate experiments, while the increase in off-current is driven by the constant accumulation of trapped holes at larger depths. In pMOS transistors, where interface traps also get positively charged, the degradation of all parameters is constant with TID, larger than for nMOS, and channel width dependent. This response is consistent across different technology nodes, which highlights the fundamental role of the STI oxide in determining the TID tolerance of MOS transistors in planar technologies with very thin gate oxide (< 5 nm).