The capability to operate at high temperature of SiC power MOSFETs makes it essential to assess radiation-induced damage under realistic operating conditions to ensure reliable evaluations of device robustness. This study investigates the total ionizing dose (TID) effects induced by X-rays at different temperatures in vertical SiC power MOSFETs. Irradiation at high temperatures results in smaller threshold voltage (VTH) degradation than at room temperature, due to enhanced recombination of positively trapped charge during exposure. Nonetheless, when high-temperature annealing is performed after the exposure, the final threshold voltage shift (ΔVTH) is independent of the irradiation temperature, and solely dependent on the temperature selected for the annealing process. The negligible degradation observed in subthreshold swing, transconductance, and C-V stretch-out indicates minimal activation of interface traps at the SiC/SiO2 interface, confirming improved interface quality in the latest generation devices.
TID Effects in Vertical SiC Power MOSFETs Irradiated at Different Temperatures
Andreetta G.;Bagatin M.;Gerardin S.;Mattiazzo S.;Paccagnella A.;Bonaldo S.
2026
Abstract
The capability to operate at high temperature of SiC power MOSFETs makes it essential to assess radiation-induced damage under realistic operating conditions to ensure reliable evaluations of device robustness. This study investigates the total ionizing dose (TID) effects induced by X-rays at different temperatures in vertical SiC power MOSFETs. Irradiation at high temperatures results in smaller threshold voltage (VTH) degradation than at room temperature, due to enhanced recombination of positively trapped charge during exposure. Nonetheless, when high-temperature annealing is performed after the exposure, the final threshold voltage shift (ΔVTH) is independent of the irradiation temperature, and solely dependent on the temperature selected for the annealing process. The negligible degradation observed in subthreshold swing, transconductance, and C-V stretch-out indicates minimal activation of interface traps at the SiC/SiO2 interface, confirming improved interface quality in the latest generation devices.
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