We show that the performances of low cost pentacene-based organic thin-film-transistors can be optimized adjusting the pentacene growth temperature. A performance gain exceeding 10 is obtained if the pentacene is grown with a substrate temperature of 50degC instead 90degC. The saturation drain current is not a monotonic function of the pentacene growth temperature. C-V measurements performed in dark conditions show a negligible hysteresis, but the hysteresis is strongly enhanced if the C-V measurements are performed in light, indicating the presence of photon-activated border traps.

Organic TFT with SiO2-Parylene Gate Dielectric Stack and Optimized Pentacene Growth Temperature

WRACHIEN, NICOLA;CESTER, ANDREA;PINATO, ALESSANDRO;MENEGHINI, MATTEO;TAZZOLI, AUGUSTO;MENEGHESSO, GAUDENZIO;
2009

Abstract

We show that the performances of low cost pentacene-based organic thin-film-transistors can be optimized adjusting the pentacene growth temperature. A performance gain exceeding 10 is obtained if the pentacene is grown with a substrate temperature of 50degC instead 90degC. The saturation drain current is not a monotonic function of the pentacene growth temperature. C-V measurements performed in dark conditions show a negligible hysteresis, but the hysteresis is strongly enhanced if the C-V measurements are performed in light, indicating the presence of photon-activated border traps.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11577/2437869
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