This paper reports on an extensive analysis of the trapping processes and of the reliability of experimental AlGaN/GaN MIS-HEMTs, grown on silicon substrate. The study is based on combined pulsed characterization, transient investigation, breakdown and reverse-bias stress tests, and provides the following, relevant, information: (i) the exposure to high gate-drain reverse-bias may result in a recoverable increase in the onresistance (RON), and in a slight shift in threshold voltage; (ii) devices with a longer gate-drain distance show a stronger increase in RON, compared to smaller devices; (iii) current transient measurements indicate the existence of one trap level, with activation energy of 1.03±0.09 eV; (iv) we demonstrate that through the improvement of the fabrication process it is possible to design devices with negligible trapping. Furthermore, the degradation of the samples was studied by means of step-stress experiments, in off-state. Results indicate that exposure to moderate-high reverse bias (<250 V for LGD=2 μm) does not induce any measurable degradation, thus confirming the high reliability of the analyzed samples. A permanent degradation is detected only for very high reverse-voltages (typically VDS=260-265 V, on a device with LGD=2 μm stressed with VGS=-8 V), and consists of a rapid increase in gate leakage current, followed by a catastrophic failure. EL measurements and microscopy investigation revealed that degradation occurs close to the gate, in proximity of the sharp edges of the drain contacts, i.e. in a region where the electric field is maximum.

Trapping and Reliability assessment in d-mode GaN-based MIS-HEMTs for Power Applications

MENEGHINI, MATTEO;BISI, DAVIDE;MENEGHESSO, GAUDENZIO;ZANONI, ENRICO
2014

Abstract

This paper reports on an extensive analysis of the trapping processes and of the reliability of experimental AlGaN/GaN MIS-HEMTs, grown on silicon substrate. The study is based on combined pulsed characterization, transient investigation, breakdown and reverse-bias stress tests, and provides the following, relevant, information: (i) the exposure to high gate-drain reverse-bias may result in a recoverable increase in the onresistance (RON), and in a slight shift in threshold voltage; (ii) devices with a longer gate-drain distance show a stronger increase in RON, compared to smaller devices; (iii) current transient measurements indicate the existence of one trap level, with activation energy of 1.03±0.09 eV; (iv) we demonstrate that through the improvement of the fabrication process it is possible to design devices with negligible trapping. Furthermore, the degradation of the samples was studied by means of step-stress experiments, in off-state. Results indicate that exposure to moderate-high reverse bias (<250 V for LGD=2 μm) does not induce any measurable degradation, thus confirming the high reliability of the analyzed samples. A permanent degradation is detected only for very high reverse-voltages (typically VDS=260-265 V, on a device with LGD=2 μm stressed with VGS=-8 V), and consists of a rapid increase in gate leakage current, followed by a catastrophic failure. EL measurements and microscopy investigation revealed that degradation occurs close to the gate, in proximity of the sharp edges of the drain contacts, i.e. in a region where the electric field is maximum.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11577/2718155
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