Total-ionizing-dose (TID) effects are investigated in a highly-scaled Gate-All-Around FET technology using Si nano-wire channels of 8 nm diameter. n− and p-FETs are irradiated up to 300 Mrad(SiO2) and annealed at room temperature. TID effects are negligible up to 10 Mrad(SiO2). At ultra-high doses the TID degradation depends on the irradiation bias condition, with more severe effects observed in longer channel devices. The worst-case irradiation condition is when positive bias is applied to the gate. Threshold-voltage shifts are caused by H+-driven generation of in-terface traps at the oxide/channel interface. In contrast, FETs ir-radiated under negative gate bias are dominated by transconduct-ance loss and increases of low-frequency noise, suggesting activa-tion of border traps. Enhanced off-leakage current is observed in n-FETs due to charge trapping in shallow-trench isolation, and in p-FETs due to trap-assisted recombination at STI sidewalls and/or spacer dielectrics at drain/bulk junctions.

TID Effects in Highly Scaled Gate-All-Around Si Nanowire CMOS Transistors Irradiated to Ultra-High Doses

Bonaldo S.;Ma T.;Mattiazzo S.;Bagatin M.;Paccagnella A.;Gerardin S.;
2022

Abstract

Total-ionizing-dose (TID) effects are investigated in a highly-scaled Gate-All-Around FET technology using Si nano-wire channels of 8 nm diameter. n− and p-FETs are irradiated up to 300 Mrad(SiO2) and annealed at room temperature. TID effects are negligible up to 10 Mrad(SiO2). At ultra-high doses the TID degradation depends on the irradiation bias condition, with more severe effects observed in longer channel devices. The worst-case irradiation condition is when positive bias is applied to the gate. Threshold-voltage shifts are caused by H+-driven generation of in-terface traps at the oxide/channel interface. In contrast, FETs ir-radiated under negative gate bias are dominated by transconduct-ance loss and increases of low-frequency noise, suggesting activa-tion of border traps. Enhanced off-leakage current is observed in n-FETs due to charge trapping in shallow-trench isolation, and in p-FETs due to trap-assisted recombination at STI sidewalls and/or spacer dielectrics at drain/bulk junctions.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11577/3443474
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