Cumulative Hot-Electron Trapping in GaN-Based Power HEMTs Observed by an Ultra-Fast (10V/ns) on-Wafer Methodology

The goal of this paper is to advance the understanding of the impact of hard switching on the dynamic performance of GaN-based HEMTs. To this aim, we developed a fast (10 V/ns) on-wafer system for testing devices in hard switching. The system has been used to study the reliability of several WG = 2 mm p-type GaN HEMTs with different LGD or buffer properties. First, we show that by optimizing the drain node capacitance, we can speed-up the hard-switching transition to a few ns, even on-wafer level. Second, repeating the experiment by using multiple frequencies, from 1 kHz to 100 kHz, we demonstrate that, in real-world applications, cumulative turn-on stress has a much stronger effect on RON compared to off-state stress. Third, by comparing the results on identical devices having shorter LGD, we pinpoint hot electrons as the main mechanism in the device degradation, ruling out the contribution of self-heating. Finally, by comparing three wafers with different processing conditions (different passivation, different buffer) we suggest that trapping phenomena related to hot electrons happen in ns time scale and that the properties of the buffer can significantly impact the dynamic performance of the devices in hard switching.