This paper reports on the isolation properties and failure mechanism of n-type vertical Pt / n-GaN Schottky barrier diodes and the dependence on the drift layer doping concentration. The results indicate that (i) inde-pendently on doping density, the Schottky barrier height is lower than the theoretical expectation, and this limits the blocking properties of the junction; (ii) barrier lowering was associated to an injection mechanism that in-volves deep levels in the semiconductor layer, near the junction, favouring injection and tunneling of carriers. By performing a detailed analysis of the breakdown mechanism, we also demonstrated that (iii) the failure of the devices in reverse bias condition is related to a power-related mechanism associated to current flowing along the mesa edges. We thus conclude that (iv) a good edge termination and passivation of the surfaces is fundamental to exploit the full blocking capability of the semiconductor.

Isolation properties and failure mechanisms of vertical Pt / n-GaN SBDs

Fregolent, M;Boito, M;Marcuzzi, A;De Santi, C;Meneghesso, G;Zanoni, E;Meneghini, M
2022

Abstract

This paper reports on the isolation properties and failure mechanism of n-type vertical Pt / n-GaN Schottky barrier diodes and the dependence on the drift layer doping concentration. The results indicate that (i) inde-pendently on doping density, the Schottky barrier height is lower than the theoretical expectation, and this limits the blocking properties of the junction; (ii) barrier lowering was associated to an injection mechanism that in-volves deep levels in the semiconductor layer, near the junction, favouring injection and tunneling of carriers. By performing a detailed analysis of the breakdown mechanism, we also demonstrated that (iii) the failure of the devices in reverse bias condition is related to a power-related mechanism associated to current flowing along the mesa edges. We thus conclude that (iv) a good edge termination and passivation of the surfaces is fundamental to exploit the full blocking capability of the semiconductor.
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Utilizza questo identificativo per citare o creare un link a questo documento: https://hdl.handle.net/11577/3471061
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